IC Design

  • Why use Leventm for IC Design

  • Leventm Technologies provides the world class IC design consultancy and services right from design specification to GDS II.

Analog Design

Our Expertise

Our team of experienced design engineers have extensive experience in Analog Mixed signal design development, custom Layout.

Technology Foundation: Our team has vast hands on experience on various EDA tool sets ranging from Cadence, Mentor Graphics and Synopsys.

What we offer?

  • Analog Mixed signal design development: Power Management,Data Converters, Clocking, Modelling Solution
  • High Speed & Memory IO.
  • IO Library Development.
  • Technologies: CMOS, FinFET, SOI from 180nm to 7nm
  • Custom Layout -Design Flow:Layout Design, Layout Automation, CAD & Automation
  • Technology Foundation : Standard Cell,Memory, PDK, Memory Compiler

Standard Cell Design

Our Expertise
Our team has delivered multiple standard cell libraries at 90nm, 65nm, 45nm, 32nm, 28nm & 20nm with leading foundries. These libraries include High performance, High density, 11T, 9T, 7.5T, 6T design. We are also expert when it comes to migration of libraries to latest technologies.

What we offer?

  • Standard cell library development.
  • Process migration for older libraries.
  • Standard cell Characterization.

ASIC Design

Our Expertise
Our team of experienced design engineers have extensive SoC / ASIC / FPGA design experience from architecture to Netlist on high frequency chips in various industries – Automotive, Mobile, Design Networking, Multimedia, Processor and IoT industries.
Our team has vast hands on experience on various EDA tool sets ranging from Cadence, Mentor Graphics and Synopsys.

What we offer?

  • Feasibility Analysis
  • Architectural Definition
  • Planning/Partitioning
  • Micro-architecture design
  • RTL Coding
  • SoC Integration
  • IP/Block Development
  • Low Power Design all stages of SOC
  • ASIC Prototyping

ASIC Verification

Our Expertise
Our experienced verification team has expertise in verifying a design from scratch for various hierarchies – System / SoC / IP / Cluster / Subsystem / Block level. We are expert in performing low power, mixed-signal and HW-SW co-simulations.

What we offer?

  • System/SoC/IP/Cluster/Subsystem/Block level Verification
  • Gate Level Unit delay and SDF annotated timing simulation
  • VIP Development & Verification
  • Legacy to UVM conversion
  • SOC level/Block level Testbench development
  • Formal Verification
  • Low Power Verification
  • Analog Mixed Signal Verification
  • Hardware & Software Co-verification
  • Post-Silicon Bring up and Validation

Backend Design & Implementation

Our Expertise

We have vast experience and expertise in place & route for block/full chip development with timing closure using industry standard tools for different stages like Synthesis, Floor Plan, Placement, CTS, Signal Integrity, IR Drop, EM, Low Power and Signoff checks.

We have extensive Knowledge in physical verification like DRC, LVS, Antenna, Density in latest nodes like 28nm, 14nm, 10nm and 7nm.

What we offer?

  • Hierarchical/Flat level chip backend Design implementation
  • Core Hardening or block Implementation
  • Die Size Estimation & Optimization.
  • Physical Verification/DFM support for Blocks and Full Chip level
  • Signoff timing closure with Cross-talk effects, OCVs
  • Timing & Functional ECO’s implementation
  • Synthesis/Formal equivalence
  • Low Power Design/UPF flow/CLP Checks Support
  • IC Packaging

FPGA Design and Implementation

Our Expertise
We offer end-to-end FPGA emulation and ASIC prototyping services. We are specialized in FPGA design, ASIC prototyping and Emulation services on various Emulation platforms. In addition, we also design custom made complex FPGA boards based on the project requirements.

What we offer?

  • Turnkey FPGA designs including documentation and verification
  • Expert device selection
  • ASIC-to-FPGA conversion
  • ASIC emulation and prototyping supporting various emulators.


Our Expertise
Our team of Engineers have vast experience in DFT insertion, Verification and silicon bring up. in various industries like Mobile, networking and Consumer Electronics.
The team has experience in vast variety of tools acorss different vendors like Mentor Graphics, Synopsys and Cadence.

What we offer? We provide Design for Test Services through:

  • Defining DFT Architecture
  • DFT Methodology Development
  • Insertion and Verification
    • Scan chains and Compression
    • Memory BIST
    • Logic BIST
    • JTAG and Boundary Scan
  • Fault Coverage improvement
  • Pattern generation and optimization
  • Constraint Definition for DFT mode
  • STA analysis in DFT mode
  • Silicon bring-up and diagnosis

Formal Verification

Our Expertise

Our experienced team has expertise in Formal verification methodologies Like Model Checking, Combinational and Sequential equivalence checking for SoC / IP / Cluster / Subsystem / Block level.

Our Expertise in analysing: Synthesis pragrmas, Cross clock Domains, X-state propagations, Tri state and bus contention, Dead Code detection, checking for case and branch enable statements and structural modelling, Verifying clock related errors.

What we offer?

  • Formal based coverage analysis, Connectivity checking using formal methods.
  • Writing specifications in the form of Assertions, Assumptions(constraints).
  • Equivalence check between RTL vs Final Signoff Netlist.
  • Sequential Equivalence check on the netlist after register re-timing, insertion of clock gating for power optimization or micro-architecture changes
  • Formally verify behavior of configuration registers for respective attributes like “read only”, “read/write” or “reset value” eliminating the need for directed tests.
  • Formally verify that secure data should not reach non-secure destinations and ensures data integrity, where non-secure data should not over-write (or reach) secure destinations.
  • Lo-Power Equivalence check between RTL vs Final Signoff Netlist

Low Power Design

Our Expertise

Our team of Engineers have vast experience in LP design and verification and Implementation expertise in SOC deign for Hand-Held Devices and Consumer Electronics.The team has experience in vast variety of tools across different vendors like Synopsys and Cadence.

We have strong expertise in various power format like UPF, CPF.

What we offer?

  • Writing UPF and CPF looking at top level SOC Power-specification.
  • Low-Power simulation and Emulation.
  • Low-Power synthesis and optimization.
  • Static low power signoff and low-Power based Logic equivalence sign-off.
  • Power Implementation and Low power aware Signal Integrity signoff.
  • Power estimation at different stages of soc design right from RTL stage.

Get in touch with us for a no-obligation analysis of your IC Design Services needs and project proposal.